The present invention relates to in general to non-volatile memory circuits, and in particular to an improved non-volatile memory circuit which employs semiconductor (i.e. MOS insulated gate) non-volatile memory elements.
In recent years, a new type of non-volatile memory element has been developed, i.e. a memory element which can store digital data even if the power source driving circuitry controlling that element is removed. This new type of non-volatile memory element is of semiconductor type, having a gate electrode to which control voltages are applied, and also source, drain and substrate electrodes, as in the case of a metal oxide semiconductor (MOS) field effect transistor, and can be formed within an integrated circuit chip together with MOS transistors and other circuit elements. With such a non-volatile memory element, applying a voltage of specific polarity and of sufficient magnitude to the gate electrode of the element will result in the threshold voltage of the element being set to a fixed value. The threshold voltage will remain at that value for a substantial period of time after removal of the high voltage from the gate electrode, even if the power source voltage of the circuit containing the non-volatile memory element is removed. If however a sufficiently high voltage of opposite polarity to that referred to above is thereafter applied to the gate electrode of the non-volatile memory element, then the threshold voltage of the element will change to become fixed at a different value, and again will remain at that value for a substantial period of time. Thus, two different states, corresponding to a single binary bit of data, can be stored by each non-volatile memory element. Data can be read out by applying a voltage of suitable value to the gate electrode of the non-volatile memory element, whereby the current state of the non-volatile memory element will be indicated by an ouput voltage appearing at the drain electrode thereof.
Such non-volatile memory elements are extremely suitable for providing a large amount of non-volatile memory capacity within an extremely small area of an integrated circuit chip, since only a very few circuit elements need be coupled to each non-volatile memory element. However with prior art circuit arrangements incorporating such elements, it has been necessary to provide a pair of terminals or connecting leads coupling the memory circuit to other circuits, with one of these terminals serving to apply a high voltage of one polarity to the gate electrodes of a plurality of non-volatile memory elements, e.g. for enabling write-in of data to the non-volatile memory elements, and the other serving to apply a high voltage of opposite polarity to the circuit, e.g. for erasing the stored contents of the non-volatile memory elements.
In order to make a non-volatile memory circuit employing such non-volatile memory elements more suitable for ultra-miniature circuit applications, it is desirable to reduce the number of externally connected terminals or connecting leads as far as possible, and this is achieved by the present invention whereby only a single input terminal need be provided to control write-in, readout and erasure of data, for a plurality of non-volatile memory elements.